Computer systems typically use inexpensive and high density dynamic random-access memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). DRAM chips are not persistent memory devices. Therefore, periodic memory refresh is needed by the DRAM chips for data retention during normal operation of the computer system. Memory refresh is a background maintenance process required during operation of semiconductor DRAM. Each bit of memory data is stored as the presence or absence of an electric charge on small capacitors which form the DRAM chips. Charges on the capacitors leak away over time, and without a memory refresh, stored data will be lost. To prevent data loss, external circuitry sends commands to cause the memory to periodically read a row and rewrite the row, restoring the charges on the capacitors of the memory cells of the row to the original charge level. While refresh is occurring, the memory is not available for normal read and write operations.
Attempts have been made to mediate the effects of refresh operations on DRAM bandwidth. Known memory controllers adopt one of two processes for refreshing DRAM. In a first example the memory controller waits until no other accesses to the memory are pending, then the memory controller provides a refresh to the memory. These are called casual refreshes. In another example, when the memory controller has waited too long, and the memory is in critical need of a refresh, and the memory controller provides urgent refreshes. Each of the foregoing examples may result in memory transactions being stalled, consequently producing a penalty in memory performance.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.